Key features

• •The CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input.
• •Very low power consumption: 70 µW (typ.) at VCO, VCO inhibit control for ON-OFF keying and ultra-low standby power consumption fo = 10 kHz, VDD = 5 V, Source-follower output of VCO control input (Demod. output), 100% tested for quiescent current at 20 V
• •Operating frequency range up to 1.4 MHz (typ.) at VDD = 10 V, RI = 5 k, High VCO linearity: <1% (typ.) at VDD = 10 V, 5-V, 10-V, and 15-V parametric ratings
• •Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V, Choice of two phase comparators: Exclusive-OR network (I) Edge-controlled memory network with phase-pulse output for lock indication (II), Zener diode to assist supply regulation, Standardized, symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
• •A Versatile Building Block for Micropower Digital and Analog Applications, Example Applications: FM demodulator and modulator, Frequency synthesis and multiplication, Frequency discriminator, Data synchronization, Voltage-to-frequency conversion, Tone decoding, FSK - Modems, Signal conditioning,